This invention relates to a pulse motor which is driven in a four-phase coil arrangement.
FIG. 1 shows a conventional pulse motor. In this pulse motor, coils 1a, 1b, 1c and 1d corresponding to A-, B-, C and D-phases are connected between a supply terminal +VM and ground, respectively, through NPN type transistors 2a, 2b, 2c and 2d. A series circuit of zener diode 3a and diode 4a, that of zener diode 3b and 4b, that of zener diode 3c and 4c and that of zener diode 3d and diode 4d are connected in parallel with coils 1a, 1b, 1c and 1d, respectively, through NPN type transistors 2a, 2b, 2c and 2d with the polarities of their diodes indicated in FIG. 1, in which case these zener diodes 3a, 3b, 3c and 3d serve as surge absorbing circuits. Coil 1a of the A-phase and coil 1c of the C-phase are wound on a common pole with their respective magnetic fluxes being excited in directions such as to cancel each other, and coil 1b of the B-phase and coil 1d of the D-phase are wound on a common pole with their respective magnetic fluxes being excited in directions such as to cancel each other, This is described in "STEPPINGMOTORS AND THEIR MICROPROCESSOR CONTROLS" by TAKASHI KENJI published from Oxford University Press in 1984.
Read only memory ROM 6 for control, random access memory RAM 7 for control, and phase output latch circuit 8 are connected to central processing unit CPU 5 via data bus 9. CPU 5 supplies phase control data and a data write signal S to phase output latch circuit 8 on the basis of program data of ROM 6. Phase control latch circuit 8, upon receipt of the data write signal S, takes the phase control data from bus line 9 for latching. Phase control signals are supplied from output terminals Ql, Q2, Q3 and Q4 of latch circuit 8 to the bases of transistors 2a, 2b, 2c and 2d, respectively.
The phase control data and data write signal S are supplied from CPU 5 to phase output latch circuit 8 at times, respectively, of FIGS. 2(A) and 2 (B). Each time the data write signal S is supplied to phase output latch circuit 8, the output signals of phase output latch circuit 8 vary as shown in FIGS. 2(C) through 2(F). That is, at a time T1 the control signals of all the phases become low, while, on the other hand, at a time T2 the control signals of the A-and B-phases become high and control signals of the C-and D-phases become low. In other words, the signals on the output terminals Q1 and Q2 of latch circuit 8 become high and signals on the output terminals Q3 and Q4 of latch circuit 8 become low. As a result, transistors 2a and 2b are turned ON to permit currents to pass through A-phase coil 1a and B-phase coil 1b. At a time T3, the signals on the output terminals Q2 and Q3 of latch circuit 8 become high and signals on the output terminals Q4 and Q1 of latch circuit 8 become low to permit currents to pass through B-phase coil 1b and C-phase coil 1c. At a time T4 the signals on the output terminals Q3 and Q4 become high and signals on the output terminals Q1 and Q2 become low to permit currents to pass through C-phase coil 1c and D-phase coil 1d. At a time T5 signals on the output terminals Q4 and Q1 of latch circuit 8 become high and signals on the output terminals Q2 and Q3 of latch circuit 8 become low to permit currents to pass through D-phase coil 1d and A-phase coil 1a. At a time T6, the signals on the output terminals Q1 and Q2 of the latch circuit 8 go high and signals on the output terminals Q3 and Q4 go low to permit currents to pass through A-phase coil 1a and B-phase coil 1b. In this way the conduction states are switched in the order of the A-and B-phases, B-and C-phases, C-and D-phases and D-and A-phases. It is to be noted that the turn-ON times of transistors 2a...2d are longer than the turn-OFF times of transistors 2 a... 2d, respectively. Now suppose that, for example, the conduction states are switched from the A-and B-phases to the B-and C-phases. At this time, transistor 2a starts to be turned OFF and, after transistor 2c has been turned ON, transistor 2a is turned OFF. At this switching time, transistors 2a and 2c are set in the ON states, simultaneously. Since at this time the A-phase coil 1a and C-phase coil 1c are wound on their common core with their respective magnetic fluxes being excited in directions such as to cancel each other, the inductance components of coils 1a and 1c cancel each other and the sum of the inductance components become zero. Thus, coils 1a and 1c possess only resistive components, permitting a flow of a larger current. If in this way such a larger current flows through the respective coil, a breakage problem occurs on transistors 2a to 2d.